The design and manufacture of semiconductor integrated circuits is well known in the art. With the many recent advances in integrated circuit technology, device dimensions are continuously decreasing while the packing density and complexity of these devices are correspondingly increasing. Coincident with these advances are also increasingly stringent requirements for electrical interconnection materials. Briefly, these requirements are low resistivity, the ability to withstand the chemicals and high temperatures used in fabrication processes, and the capability of being patterned into fine lines.
In a typical MOSFET structure, for example, an epitaxially grown single-crystal silicon layer provides a base or substrate, while polycrystalline silicon ("polysilicon") is the standard material for both gate and interconnect structures. The polysilicon is insulated from electrically conductive overlayers and the single crystal silicon substrate by layers of silicon dioxide. Although polysilicon provides the requisite stability to processing chemicals and high temperatures, a major limitation now restricting its utility as an interconnection material in high performance devices is its limited conductivity. Even heavily doped polysilicon has a conductivity of only about 300 micro-ohm-cm., thus imposing a serious limitation on circuit performance. One proposed solution has been to replace polysilicon with pure metals such as aluminum, tungsten or titanium, which have a conductivity far higher than that of polysilicon. However, these materials are also limited in that they may react with the silicon substrate at the high temperatures used in integrated circuit fabrication and may additionally be unable to withstand the chemical reagents used in processing.
An alternative solution has been the incorporation of refractory metal silicides into integrated circuit fabrication technology. Silicides offer several advantages over single-layer doped polysilicon. In contrast to doped polysilicon, which at a typical thickness of 4500 angstroms has a sheet resistivity of 15 ohms per sheet or more, silicides provide on the order of 2 ohms per sheet or less. Tantalum and tungsten silicides each have sheet resistivities of about 2 ohms per sheet, molybdenum silicide about 1.5 to about 2.0 ohms per sheet, and titanium silicide about 0.5 ohms per sheet. Silicides are also compatible with MOSFET and other integrated circuit fabrication processes as they can generally withstand high temperatures and caustic processing chemicals. Finally, providing there is sufficient silicon underlying the silicide layer, a self-passivating silicon dioxide layer can be thermally grown over the silicide without any degradation of chemical or electrical properties of the silicide film.
Metallic silicides provide the desired resistivity and the chemical and thermal stability necessary for use as interconnects, and they function well as FET gates. A layered structure having a polysilicon layer sufficiently thick to serve as a transistor gate, underlying the silicide, is often used. These "polycide" structures have resistivities on the order of 4 ohms per sheet or less where the combined thickness of both layers is about 4500 angstroms. The use of such polycide structures is fairly recent but is known in the art. U.S. Pat. No. 4,180,596 to Crowder et al., for example, discloses a method of providing a silicide layer on a polysilicon substrate by means of sputtering and subsequent annealing. U.S. Pat. No. 4,468,308 to Scovell et al. shows a method of providing a silicide layer on a semiconductor substrate using a vapor deposition technique. Other semiconductor circuit structures having silicide layers include those disclosed in the following: U.S. Pat. No. 4,276,557 to Levinstein et al., which shows a tantalum or titanium silicide layer sandwiched between a layer of doped polysilicon and a vapor-deposited layer of silicon dioxide; U.S. Pat. No. 4,332,839 to Levinstein et al. and U.S. Pat. No. 4,337,476 to Fraser et al., which show a silicide layer interposed between a layer of polysilicon and a thermally grown layer of silicon dioxide; and U.S. Pat. No. 4,450,620 to Fuls et al., which shows an MOS integrated circuit device having both silicide and polysilicon layers.
One problem noted in the fabrication of polycide structures is poor adhesion of the silicide layer, both during silicide formation and in subsequent fabrication processes. During silicide formation, volume shrinkage can result in large tensile stresses in the range of 1-3.times.10.sup.10 dynes per square cm. Because the coefficients of thermal expansion for silicides and polysilicon differ substantially, the high temperatures used in subsequent fabrication processes such as annealing can cause additional stress. Furthermore, cracking and delamination can occur during etching as well.
One proposed solution to the problem is the use of dual target sputtering in silicide formation, where both the silicide and the silicon targets are subjected to the same sputtering conditions. Such a system is shown, for example, in U.S. Pat. No. 4,443,930 to Hwang et al. While this system is effective in reducing tensile stress during formation of silicide, cracking and delamination can nevertheless occur in later fabrication processes. The solution proposed by the method of this invention addresses this latter problem, and relates to ion implantation of the silicide layer as a stress reduction technique.
Ion implantation offers a number of advantages as a method of introducing impurities into a host material. Among these advantages are: (1) precise control over the number of impurities implanted; (2) low temperature operation; (3) complete introduction of impurities below the host surface; and (4) control over the depth of implantation. The use of ion implantation as a method of doping silicon during device fabrication is well known. U.S. Pat. No. 4,373,251 to Wilting, for example, shows a polycide structure having a polysilicon layer doped by means of ion implantation. U.S. Pat. No. 4,450,620 to Fuls et al. similarly shows the use of ion implantation to dope the polysilicon layer of a polycide structure. The use of ion implantation to dope silicide and thereby reduce tensile stress and corresponding cracking and delamination problems is, however, novel.